Bipolar transistors, integrated in a substrate, can be manufactured in self-aligned double silicon processes, as discussed in, for example, T. H. Ning et al., IEEE Trans. on Electron Devices, Vol. 28 (1981), and G. P. Li et al., IEEE Electron Device Letters, Vol.8 (1987). In such a manufacturing process, two oppositely doped polysilicon layers are successively applied onto a substrate. A base terminal arises from a first polysilicon layer, while emitter and collector terminals arise from a second polysilicon layer. The two polysilicon layers are separated by an oxide spacer. An oxide spacer is an insulating edge cover, produced either at the finished base terminal prior to the application of the second polysilicon layer, or at the finished emitter terminal prior to the application of the first polysilicon layer. As a result, the spacing between the base and emitter terminals becomes independent of the photolithographic process used.
One disadvantage of the above method is the extremely uneven topography of the resulting bipolar transistors, which is disadvantageous in LSI circuitry. Additionally, the above method requires re-etching steps when structuring the first polysilicon layer, and when forming oxide spacers. During the re-etching process, the substrate surface is eroded, resulting in a loss of the reference plane. Consequently, connecting problems arise in transistors manufactured in accordance with the above method.
A further disadvantage of the above method is that a plasma-assisted etching of the resulting emitter boundary surface is required when forming the spacers at the side walls of the base terminal, as well as when structuring the first polysilicon layer. Such plasma-assisted etching results in yield risks.
Moreover, the manufacture of transistors having oxide spacers at the side walls of the base terminals is not compatible with advanced technologies, such as deposited homobases, heterobases, or heteroemitters.
In addition, when the emitter terminal is manufactured first, and oxide spacers are used to cover the side walls of the emitter terminal, it is impossible to implement a selfaligned pedestal collector, which has an additional implantation of the collector in the active transistor region. Such pedestal collector is discussed in K. Ehinger et al., ESSDERC'89, (1989).
Yet another disadvantage of the above method arises from the difficulties of introducing silicide techniques for both the first and second polysilicon layers. When introducing silicide techniques, one of the silicides must withstand a high-temperature step without damaging the properties of the component. Thus, where the base terminal is produced first, and covered with oxide spacers, the silicide of the base terminal must withstand temperature steps during the out diffusion of donors for emitter formation without damage. On the other hand, when the emitter terminal is produced first, and provided with spacers, the silicide of the emitter terminal must withstand the temperature steps during the manufacture of the base terminal.